1. Field of the Invention
The present invention relates to determination of critical area and, more particularly, to a method and system for computing critical areas for predicting yield for semiconductor devices.
2. Description of the Related Art
Critical area of a very large scale integration (VLSI) layout is a measure that reflects the sensitivity of the layout to defects occurring during the manufacturing process. Critical area is widely used to predict the yield of a VLSI chip. Yield prediction is essential in today's VLSI manufacturing due to the growing need to control cost. Models for yield estimation are based on the concept of critical area which represents the main computational problem in the analysis of yield loss due to spot defects during fabrication. Spot defects are caused by particles such as dust and other contaminants in materials and equipment and are classified into two types: "extra material" defects causing shorts between different conducting regions and "missing material" defects causing open circuits.
Extra material defects appear most frequently in a typical manufacturing process and are the main reason for yield loss. The yield of a chip, denoted by Y, is computed as ##EQU1##
where Yi is the yield associated with the ith step of the manufacturing process. The yield of a single processing step is modeled as ##EQU2##
where d denotes the average number of defects per unit of area, .alpha. the clustering parameter, and A.sub.c, the critical area. Extra material defects has been addressed in detail in a related commonly assigned disclosure, application Ser. No. 09/156,069 now U.S. Pat. No. 6,178,539 B1, incorporated herein by reference for all purposes.
For a circuit layout C, the critical area is defined as ##EQU3##
where A(r) denotes the area in which the center of a defect of radius r must fall in order to cause circuit failure and D(r) is the density function of the defect size. The defect density function has been estimated as follows: ##EQU4##
where p, q are real numbers (typically p=3, q=1), c=(q+1)(p-1)/(q+p), and r.sub.0 is some minimum optically resolvable size.
Using typical values for p, q and c we derive the widely used defect size distribution D(r)=r.sup.2.sub.0 /r.sup.3. Since r.sub.0 is typically smaller than the minimum feature size, D(r) is ignored for r&lt;r.sub.0).
Missing material defects cause open circuits by breaking intended connections. For example, on a metal interconnect layer an open is created by a defect breaking the continuity of an interconnection or a contact plug; on a via or contact layer an open is a defect destroying a contact. Thus, two types of missing material defects can be distinguished: breaks, interfering with the continuity of an interconnect, and via-blocks, destroying contacts on via layers. Critical area may be computed independently for each type of defect.
Existing methods of extracting critical area for opens can be summarized as follows:
1. Monte Carlo simulation: Draw a large number of defects with their radii distributed according to D(r), check for each defect if it causes an open circuit, divide the number of defects causing faults by the total number of defects to derive the probability of fault.
2. Geometric methods: Compute the area of critical region A(r) for several different values of r independently; use the results to approximate the total critical area. Opens are treated geometrically without considering actual breaks of connectivity. These methods are usually based on shape manipulation tools providing operations such as shrink-shape-by-r and find-area techniques. The time complexity for each defect radius depends on the underlying shape manipulation algorithms. A(r) may also be computed using a more efficient scan-line method.
3. The grid method of one prior art technique assumes a fine grid over the layout and computes the critical radius (The critical radius at point t is the radius of the smallest defect centered at t causing an open) for every grid point. The method is given for shorts; opens are treated as the dual problem. The run-time is 0(I.sup.1.5) time, where I is the number of grid points. A more thorough analysis to critical area for missing materials is given by J. S. Rogenski in "Extraction of Breaks in Rectilinear Layouts by Plane Sweeps," Technical Report, Univ. of California, Santa Cruz, UCSC-CRL-94-21, April 1995.
4. A(r) for a given defect radius r, may also be calculated strictly over each shape (critical regions expanding in the free space are ignored). The critical region in one shape is assumed to be produced by broken edges on the same shape. The algorithm uses plane sweep and builds connectivity graphs for each node. This method (unlike the geometric ones) considers actual breaks of connectivity and runs in 0(n.sup.2 log n) time.
The prior art methods described above require high computation times, and even then do not accurately compute critical area. The existing geometric methods compute the area of the critical region for only one defect size and require higher time complexity.
The above approaches suffer from accuracy and complexity problems as described. Therefore, a need exists for an improved approach for computing the critical area for opens in a single layer of a semiconductor device. A further need exists for a low polynomial algorithm for computing critical area for opens with improved accuracy and reduced complexity.